1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device capacitor, and more particularly, to a method of manufacturing a semiconductor device capacitor having an improved alignment margin and capacitance.
2. Description of the Related Art
The demand for increased integration of semiconductor devices typically requires an increase in the capacitance of semiconductor capacitors incorporated in the devices. As a result, the structure of semiconductor capacitors is becoming more complicated.
In semiconductor memory devices, one unit cell of Dynamic Random Access Memory (DRAM) comprises a single capacitor and a single transistor. The demand for increased integration of semiconductor devices dictates that the capacitance of the capacitor increases while the size of the unit cell decreases. Even if the area of a capacitor is decreased, the capacitor must continue to have a capacitance sufficient to store adequate charge. However, decreasing the area of the capacitor tends to decrease the area of the storage electrode, which causes problems in the limit of the alignment margin between the storage electrode and the contact holes under the storage electrode.
One way to address the difficulty associated with decreasing alignment margins, is to reduce the size of the contact holes instead of reducing critical dimensions for the pattern used to form the storage electrode. However, due to limitations in current photo-lithography process technology, it is very difficult to decrease the size of the contact holes.
FIGS. 1 and 2 are cross-sectional views illustrating problems associated with a conventional method of manufacturing a semiconductor capacitor. Referring to FIG. 1, a polysilicon layer 12 for the storage electrode is formed on the semiconductor substrate 2 having a lower structure 4 of a nitride film 6, an oxide film 8, and a bit line 5. A photoresist pattern 14 for the formation of the storage electrode is formed by a typical photo-lithography process. More particularly, contact holes 10 are first formed over the semiconductor substrate 2 including the lower structure 4 of nitride film 6, oxide film 8, and bit line 5 by a photo-etch process, and polysilicon layer 12 is formed by Low Pressure Chemical Vapor Deposition (LPCVD), thus burying contact holes 10.
Photoresist is then coated on the polysilicon layer 12 and a photoresist pattern 14 is formed by using a photo-lithography process.
As described above, with highly-integrated DRAM devices, the critical dimensions of photoresist pattern 14 for the formation of the storage electrode of the capacitor are becoming smaller, decreasing the alignment margin of photoresist pattern 14 and contact holes 10. In the formation process for the capacitor, the alignment of photoresist pattern 14 for the formation of the storage electrode and contact holes 10 is an important factor and is closely related to the capacitance of the capacitor. Therefore, after forming photoresist pattern 14, the alignment state of photoresist pattern 14 and contact hole 10 is measured using an alignment measuring device. Based on the extent of measured misaligned values, photoresist pattern 14 on semiconductor substrate 2 may be removed, and another photo-lithography process performed for the formation of photoresist pattern 14. Alternatively, if the misaligned values are acceptable, the next step in the device formation may be carried out.
As shown in FIG. 1, the misalignment (M1) between the photoresist pattern 14 and the contact holes 10 continuously affects the etch process for the polysilicon layer 12, thereby causing misalignment (M1) between the contact holes 10 and the storage electrode formed after the etch process for the polysilicon layer 12.
FIG. 2 is a cross-sectional view showing storage electrodes 12a, 12b, and 12c formed by the etch process for the polysilicon layer 12 using the photoresist pattern 14 as an etch mask. The etch process is carried out in an etch chamber. Storage electrodes 12a, 12b, and 12c are formed by a dry etching process using the photoresist pattern 14 as an etch mask.
The storage electrodes 12a, 12b, and 12c store their information based on charge transferred from the source region of the transistor through the contact holes 10. Oxide film 8 contained in the lower structure 4 of the semiconductor substrate 2 is used as an intermediate insulating layer. It should be apparent to those skilled in the art that the shapes and the structure of the storage electrodes 12a, 12b, 12c can be altered.
FIG. 3 is a cross-sectional view of FIG. 2 taken along the line III-III'. As shown in FIG. 2 and FIG. 3, when the etch process generates misalignment (M1) between contact holes 10 and photoresist pattern 14, the polysilicon layer 12 inside the contact holes 10 is exposed to etch gas proportional to the misalignment (M1) of the contact holes 10 and the storage electrode 12c. Etching of the exposed polysilicon layer forms empty holes 18 within the contact holes 10. An empty hole 18 increases the contact resistance of the storage electrode, increasing the likelihood of the storage electrode breaking and decreasing the reflash characteristics of the capacitor.
Therefore, there is a need in the art to overcome the above problem with the photo-lithography process and, in particular, to solve the misalignment problem between the storage electrode and the contact holes.